Half Clock assertion check?

SystemVerilog
, ,
1

Hi,
I have a assertion check requirement:

Lets say that the Signal A remains high from reset, It goes low for enabling a block:
As the signal goes low that block’s clk is enabled and it starts to toggle.

The delay between signal A going low and the Clk getting enabled is T/2.

To explain further:
Clk can go either from low to high OR high to low
The T/2 is the timeperiod of clk itself. (Delay between A going low and the Clock getting triggerred)

Code Below for Reference:

always @*
case (clk_freq[1:0])
00: half_max_dly = 25;
01: half_max_dly = 50;
10: half_max_dly = 100;
11: half_max_dly = 200;
endcase

always @(negedge A) begin
T1 = $time;
end
// This would trigger everytime
always @(CLK) begin
T2 = $time - T1;
end

half_clk_check : assert property (@(T2)
T2 <= half_max_dly)
else $error(“half_clk_check Condition unmet”);

Please suggest accordingly for corrections as my assertion checks multiple times.

Ravi

2

I am not a expert on Assertions but, atleast i would have done it a little differently.

property half_period_check(BLOCK_ENA, SIG_A)
@(posedge BLOCK_ENA) disable iff(~RESETn)
(`TRUE, t1=$time) |=> @(negedge SIG_A) (($time - t1) == HALF_CLK_TIME);

BLOCK_ENA – is your block enable.
SIG_A – is the signal A which should go low after BLOCK_EN goes high.
HALF_CLK_TIME – you can calculate period and keep this variable or you can define as a parameter.

–Skumar