Global define UVM_REG_DATA_WIDTH

UVM
, ,
3

In reply to Tudor Timi:

Thanks,
I am unable to get the uvm_reg to generate the correct address for accessing my uvm_mem “MEM_winhashmem”. Details below.

Here is my code.

  1. I have defined ‘+define+UVM_REG_DATA_WIDTH=512’ since some register X is 512b wide.
  2. I have a memory “MEM_winhashmem” that is 16K * 512b starting at offset 0x80000 I use a vreg to access it.
    My Model
    =========
    rand my_uvm_mem MEM_winhashmem;
    rand my_uvm_vreg winhashmem;

virtual function void build();
this.MEM_winhashmem = new(“MEM_winhashmem”, 16384, 64);
this.MEM_winhashmem.configure(this);
this.winhashmem = new;
this.winhashmem.configure(this, MEM_winhashmem, 16384);
this.winhashmem.build();
this.default_map.add_mem(this.MEM_winhashmem, `UVM_REG_ADDR_WIDTH’h80000);

My Sequence

task body();
regmodel.winhashmem.write(0, status,512’hF000DCAFE); // Generates address 0x80000
regmodel.winhashmem.write(16383, status, 512’hAA55BBCC); // Generated address 0x17ffc0
endtask

Problem

since the memory is only 64b wide, I expected the address of index 16383 = 0x80000 + 0x1fff8 = 0x9FF8

However I am getting 0x80000 + 0x40 *16383 = 0x17FFC0. This is not correct.

-sanjeev