Getting syntax error, need solution

SystemVerilog
,
1

I’m trying to compile the below code. But getting a compilation error. I don’t see any issue in my code. Can someone help me to resolve compile error?


// Code your testbench here
// or browse Examples
class packer_base;
  int a ;
endclass

class packet;
  int b;
  packer_base p;
  
  function new();
    p = new();
  endfunction
  
  function display();
    $display("value of a = %d , b = %d",p.a,b);
  endfunction
  
endclass

module my_class;
  
  
  packet p1; 
  packet p2;
  
  
  p1 = new();
  p1.b = 10;
  p1.p.a=5;
  
  p2 = new p1;
  
  p1.display();
  p2.display();
  
endmodule

Error I’m getting is :
Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 28: token is ‘=’
p1 = new();

2

In reply to ravitejavoora:

Procedural code needs to be put into an procedural block

initial begin
 p1 = new();
  p1.b = 10;
  p1.p.a=5;
 
  p2 = new p1;
 
  p1.display();
  p2.display();
end