Getting issues in Compiling UVM Hello world code in Questasim10.3d

UVM
,
4

In reply to dave_59:

Please find my code below

////////////////////////////////////////////////////////////////////////////
include "uvm_pkg.sv" include “uvm_macros.svh”
module top;
import uvm_pkg::*;
class ahb_uvm_test extends uvm_test;
uvm_component_utils(ahb_uvm_test) function new(string name,uvm_component parent); super.new(name,parent); endfunction //task run_phase(uvm_phase phase);' task run_phase(uvm_phase phase); uvm_info(“TEST”,“In test run phase”,UVM_LOW);
endtask
endclass
initial begin
`uvm_info(“TOP”,“Simulating the test”,UVM_LOW);
run_test(“ahb_uvm_test”);
end
endmodule
////////////////////////////////////////////////////////////////
My command:
vsim work.top +UVM_TEST_NAME=ahb_uvm_test -L /tools/qsim-10.3d/verilog_src/uvm-1.1d

I am getting below issue
Error: (vopt-19) Failed to access library ‘/tools/qsim-10.3d/verilog_src/uvm-1.1d’ at “/tools/qsim-10.3d/verilog_src/uvm-1.1d”.

Thanks
Bharath