Genvar variable query

SystemVerilog
1

Hi,
I have code as shown below

module tb;
int b;
--------
--------
-------
generate
for(genvar i=0;i<b;i++)
------
--------
endgenerate

Error: Illegal non-constant generate loop condition.
Iam getting error with the above code. Can someone give me solution for this? b varies time to time

2

In reply to janudeep3:
The genvar works only with constant value or parameter.
Here, you can use a parameter instead of a variable. Check the example program at below link.
http://www.edaplayground.com/x/7bm
In this example, parameter P is overridden from value 2 to 5. I think it may fulfill your requirement of using variable b.

BTW, what is your purpose for using a generate block?

3

In reply to bdreku:

Hi

I got the above thing but my b varies in between the simulation also. Iam using generate in assertions.

4

In reply to janudeep3:
Have you tried fork join and automatic inside for loop?
e.g.

for(int i=0; i<b; i++) begin
   fork
     automatic int j = i;
     ...
     ...
   join_none
end