Generic clock generation in System Verilog

UVM
,
1

Hi,
I am willing to generate a generic clock generator. It should generate ‘n’ number of clocks simultaneously.I have written a logic but its not working, can anyone please help me.
Here is the code snippet

task clock_;
fork
for(int i=0; i< no_of_clks ;i=i+1) begin
clk_gen(i);
end
join
endtask

task automatic clk_gen(input int i);
…CLK generation logic
endtask

2

In reply to perumallatarun:

You want to use the fork/join_none inside of your for() loop:


task clk_;
for( int i=0; i<no_of_clks;i=i+1)
  fork
    automatic int j=i; // local copy, j, for each value of i
    clk_gen(j);
  join_none
endtask
3

In reply to cgales:

Thank you cgales. Its working.