Generic clock generation in System Verilog

In reply to perumallatarun:

You want to use the fork/join_none inside of your for() loop:


task clk_;
for( int i=0; i<no_of_clks;i=i+1)
  fork
    automatic int j=i; // local copy, j, for each value of i
    clk_gen(j);
  join_none
endtask