I am trying to generate the random clock period and random clock duty cycle. I am having the code as below. But facing some compilation errors.
Say I require random clock period i got 2ns and duty cycle as 20%. It means i need to generate the clock with 1ns time period and 20% duty cycle.
Like wise, my code should be generalized in such a way that it can support the clock period in b/w 1ns to 10ns and duty cycle in b/w 10% to 20%.
class random_clock_generator;
rand int duty_cycle, clock_value;
constraint clock_range{solve (clock_value inside{[0.000000001:0.0000000001];})before (duty_cycle inside{[0.1:0.9];});}
endclass:random_clock_generator
module abc();
random_clock_generator rcm_1;
float a,b;
int clk =0;
initial begin
rcm_1 =new();
rcm_1.randomize();
a = rcm_1.duty_value;
b = 1-a;
forever begin
#a clk = ~clk;
#b clk = ~clk;
end
end
endmodule
Error I am getting
Error-[SE] Syntax error
Following verilog source has syntax error :
variable type is not user defined type
"clock_generator_with_different_duty_cycle.sv", 4: token is 'duty_cycle'
rand float duty_cycle, clock_value;
The variables duty_cycle and clock_value are integers. How do you expect to constrain them to be inside real values? The rand qualifier and constraint values can only be used with integral values.
You should randomize integral values and then convert them to delay values after randomization.
In reply to Manikanta Kopparapu:
The variables duty_cycle and clock_value are integers. How do you expect to constrain them to be inside real values? The rand qualifier and constraint values can only be used with integral values.
You should randomize integral values and then convert them to delay values after randomization.
If i give the rand qualifier as float I am getting the following error.
Error-[SE] Syntax error
Following verilog source has syntax error :
variable type is not user defined type
"clock_generator_with_different_duty_cycle.sv", 4: token is 'duty_cycle'
rand float duty_cycle, clock_value;
If i give the rand qualifier as real also i am getting the error.
Error-[SE] Syntax error
Following verilog source has syntax error :
"clock_generator_with_different_duty_cycle.sv", 7: token is '('
constraint clock_range{solve (clock_value
inside{[0.000000001:0.0000000001];})before (duty_cycle inside{[0.1:0.9];});}
I would appreciate if you share the pseudo code for the conversion of integer values to real values .
Thanks!
class random_clock_generator;
rand int duty_cycle, clock_value;
real duty_cycle_real, clock_value_real;
constraint clock_range {
clock_value inside{[1:10]};
duty_cycle inside{[1:9]};
};
function void post_randomize();
duty_cycle_real = duty_cycle/10.0; // floating point division
clock_value_real = clock_value * 1ps; // convert integer to scaled delay
endfunction
endclass:random_clock_generator
Other notes: the solve before construct is used between variables, not constraints. And it only makes sense to use when there are constraint dependancies between the variables. See this.