Generate specific clock slow down the simulation

SystemVerilog
, ,
1

I have to generate multiple clock in my top (testbench).

The simulation ran ok until I added the following code:

 initial begin
      tb_pcie_clk_q0p = 1'b0;
      forever begin
     #5ns;  //100MHz (half cycle)
     tb_pcie_clk_q0p = ~tb_pcie_clk_q0p;         
      end      
   end
   assign tb_pcie_clk_q0n = ~tb_pcie_clk_q0p;

In addition I have already had other clocks like:

initial begin
      tb_fpga_clk = 1'b0;
      forever begin
         #4ns; //125 MHz
         tb_fpga_clk = ~tb_fpga_clk;
      end
   end

 assign tb_clk = dut.clk_rst_ctrl_i.clk_250;
2

What is the issue you are facing??

3

In reply to Chandra Bhushan Singh:

When I add the code for the pci_clk the simulation slows.

4

In reply to saritr:

I guess this is not the real problem. You are proving clock to your PCIe RTL previously which you are not providing I guess so more event scheduling is happening and taking more time to complete the function simulation .