Generate block and Macro combination

SystemVerilog
1

Hello,

i want to pass an argument to macro from generate block but getting an error. please find the code

define DATA_CHECK(intf,num,rem)\ MY_ASSERTION(data_intfo,ennumi,cntrrem_i)

generate
for(genvar i = 0; i< 31; i++)
begin
`MY_ASSERTION(i,(i/4),(i%4))
end
endgenerate

but getting compilation error as ‘en_ /4_o’ is not defined. but i want for i = 2 en_0_i and cntr_2_i. as MY_ASSERTION Macro
Is there any solution for above issue.

Thanks in advance.
Mitesh N Patel

2

In reply to mitesh.patel:

It is difficult to get an idea from this code. I think there maybe some issue with back-ticks (`). Can you provide a minimal code where you get this error? (MCVE).

3

In reply to mitesh.patel:

Hello,
i want to pass an argument to macro from generate block but getting an error. please find the code
define DATA_CHECK(intf,num,rem)\ MY_ASSERTION(data_intfo,ennumi,cntrremi)
generate
for(genvar i = 0; i< 31; i++)
begin
`MY_ASSERTION(i,(i/4),(i%4))
end
endgenerate
but getting compilation error as 'en /4_o’ is not defined. but i want for i = 2 en_0_i and cntr_2_i. as MY_ASSERTION Macro
Is there any solution for above issue.
Thanks in advance.
Mitesh N Patel

I don’t think that you can use macro for this purpose. The macro will replace ‘num’ by exactly string ‘i/4’ (instead of i/4 value), therefore you will get error because ‘en_i/4_o’ is not defined. If you want to use this macro, you have to call `DATA_CHECK for every value of i:


`DATA_CHECK(0, 0, 0);
`DATA_CHECK(1, 0, 1);
`DATA_CHECK(2, 0, 2);
...

otherwise please find other ways.

4

In reply to mitesh.patel:

See Combination of generate and macro | Verification Academy

5

In reply to sharvil111:
Thanks sharvil111,dave_59 and cuonghl.

here ASSERTION_INPUT_DATA_CHECK is macro with enables other macros of my code.

define DATA_CHECK(flow,intf_num,skew)\ ASSERTION_INPUT_DATA_CHECK(data_flowi,clk_i,clk_o,enintf_numo,cntrlintf_num_o,skew,0,flow)

//DATA_CHECK(12,3,0); // It is working fine if i used fix numbers generate for(genvar flow=0; flow < 64; flow ++) begin DATA_CHECK(flow, flow/4 flow%4);
end
endgenerate

if any possible way are there please suggest.