[Formal] SVA: how to localize assumptions for a particular SVA

SystemVerilog
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2

In reply to ssureshgverifier@gmail.com:
In SVA you can use the assertion controls

$assertcontrol ( control_type [ , [ assertion_type ] [ , [ directive_type ]
[ , [ levels ] [ , list_of_scopes_or_assertions ] ] ] ] ) ;
let ON = 3; // assertion control type
let OFF = 4; // assertion control type
let CONCURRENT = 1; // assertion_type, concurrent
let ASSUME = 4; // directive_type for assertion control tasks
/* levels: This argument specifies the levels of hierarchy, consistent with the corresponding
argument to the $dumpvars system task (see 1800-2012 section 21.7.1.2). If this argument is not specified, it defaults to 0 (i.e., the specified module and in all module instances below the specified module). 
Example: $dumpvars (1, top); // Because the first argument is a 1,
// this invocation dumps all variables within the module top;
// it does not dump variables in any of the modules instantiated by module top. */
//
event start_sim; // /ch4/4.2/assertion_control.sv
int count1=0, count2=0;
ap_x1: assert property(Px1) count1 <= count1 + 1'b1;
ap_x2: assert property(Px1) count2 <= count2 + 1'b1;
initial begin
$assertcontrol(KILL); // Stop checking all assertions
wait (start_sim); // wait for subsystem to be ready to start checking for assertions
$assertcontrol(ON); // enable all assertions
// disable all pass action blocks except those needed
$assertcontrol(LOCK, ALL_ASSERTS, ALL_DIRECTIVES, 0, ap_x1); // lock any changes to ap_x1
$assertcontrol(PASSOFF); // pass off for ap_x2
$assertcontrol(UNLOCK, ALL_ASSERTS, ALL_DIRECTIVES, 0, ap_x1, ap_x2);

I explain all of this in my SVA book.
This link provides those pages on that topic
http://systemverilog.us/vf/assertion_cntrl.pdf

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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