Forever loop in fork_any : Understanding terminating condition

SystemVerilog
, ,
1 


fork
///process-1
     begin
       forever begin
         @(posedge monitor_virtual_interface.SCLK or negedge monitor_virtual_interface.SCLK)begin
         	if(!monitor_virtual_interface.PL)
            	begin
              		monitor_clk = monitor_virtual_interface.SCLK;
            	end
          end
        end
     
     end
///process-2
      begin
        forever begin
          @(posedge monitor_clk)begin
            if(!monitor_virtual_interface.PH)begin 	
              AUX = {monitor_virtual_interface.MOSI, AUX[7:1]};
              AUX2 = {AUX2[6:0],monitor_virtual_interface.MISO };	           
            end
          end
        end
      end
      join_any

This is a code extract from a VIP for SPI UVM Monitor I have been trying to understand.
When does the code exit the fork-join_any construct? My simulation could have multiple data bytes being driven which are being accounted for in the forever construct which waits for every single data byte to be received. Lets says I send a data byte, insert a delay of #10000 and then send another data byte. It means that the code should never exit from the forever construct, keep waiting for new data bytes and so my simulation will never end. Is my understanding correct?

2

In reply to rejoymathews32:

UVM drivers and monitors are typically designed to run forever. The generation of stimulus is controlled by the sequences, so the drivers and monitors need to be able to handle stimulus throughout the entire simulation run.

When all test sequences are complete and test objections are dropped in the run_phase(), the UVM scheduler will kill all threads forked, which will include the driver and monitor tasks.