Forcing the DUT signal

SystemVerilog
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1

Hi,
As we all know that in our UVM based verification environment in TOP there is a DUT and under this Test will Come. Now If we want to force the DUT signal from test without using Interface, can some explain me how can we achieved this.

2

https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection

3

In reply to dave_59:

Thanks Dave. But need more clarification as in your paper we are still using the interface for DUT signal.
Suppose i want to force the dut signal as:
signal name is reset_b;
Model name is adder;
signal reside in added.adder_1.

so if we want to force the signal from test case we can used this as:
force (“adder.adder_1.reset_b”, 1’b0")
??

4

In reply to yuvraj khare:

You can’t use a string to represent a hierarchical path. You can use an interface or module with a bind statement to connect to the DUT signal as the paper shows using the bind statement. Instead of a set/get_probe method, you can have a force method that testbench can call.

5

In reply to dave_59:

Thanks Dave.