Forcing the DUT signal

SystemVerilog
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3

In reply to dave_59:

Thanks Dave. But need more clarification as in your paper we are still using the interface for DUT signal.
Suppose i want to force the dut signal as:
signal name is reset_b;
Model name is adder;
signal reside in added.adder_1.

so if we want to force the signal from test case we can used this as:
force (“adder.adder_1.reset_b”, 1’b0")
??