Force a DUT signal from a systemverilog class

In reply to chr_sue:

bind is used for many things besides assertions. It’s just that the one example of using it in the LRM happens to be with an assertion. This is no coincidence because the construct came out of a requirement for people adding assertions.

See this link for another example as well as my DVCon paper which shows how to integrate a UVM testbench with a bound interface.