Force a DUT signal from a systemverilog class

In reply to chr_sue:

I agree that ‘bind’ is used for doing assertions - I do it all the time.

Normally testbenches have the driver at the top-level of the testbench. In fact, I don’t know anyone doing anything different. Even if you’re doing ‘harnesses’, the driver is instanciated in the top-level testbench.

My note was that I suspect that (in theory) there would be a way to do the ‘force’ from within the bind, I also suspect that the vendors haven’t verified their SW does it properly, so I’d not use it. I try to stick to the “main path” on tool features. Just because a feature is in the LRM, doesn’t mean it’s well-supported by the vendor(s).

So I think we are in “violent agreement” on the use of ‘bind’ and where to put UVM drivers.