For Dpram . how i can write a constraint block using both random write and random read signals such that write should come first and later read signal

SystemVerilog
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4

In reply to juhi_p:

I got to know couple of new things here one is %p which I didn’t know and second thing is usage of const’ in the constraint … thank you … Now I have a question, if you look at the first two lines of the output below in the second line it is trying to read from address 2 but it has never written to that address before… so how is the write before read condition satisfied ??

'{w_addr:3, r_addr:1, w_data:2, w_en:1, r_en:0, r_data:0, cnt:0, flag:0}
'{w_addr:2, r_addr:2, w_data:1, w_en:0, r_en:1, r_data:0, cnt:0, flag:0}