Flow after run_test() is executed

UVM
,
1

Hi all,

I am getting an error like Error (suppressible): (vsim-3601) Iteration limit 10000000 reached at time 0 ns.

By just running the UVM testbench am getting above mention error and no DUT is attached to it. if i get to know the flow then it may help in debugging it.

2

In reply to anilhr:

Hi,

I assume that you have somewhere an endless loop which consumes some delta cycles. I obtained the same error with this example:


`include "uvm_macros.svh"
import uvm_pkg::*;

class my_test extends uvm_test;
   `uvm_component_utils(my_test);

   function new(string name = "", uvm_component parent);
      super.new(name, parent);
   endfunction

   task run_phase(uvm_phase phase);
      phase.raise_objection(this, $sformatf("Start of test: %s", get_name()));
      forever begin
         #0;
      end
   endtask
endclass

module top;
   initial begin
      run_test("my_test");
   end
endmodule

Can you confirm that your code contains such a loop?

Best regards,
Cristi

3

In reply to Cristian_Slav:

my test is more complicated than above code, But yes i have forever loops in my code.

4

In reply to anilhr:

Try to look in those loops to make sure they consume simulation time.

5

In reply to Cristian_Slav:

What I usually do in this situation is stop the simulator and print the call stack. Then you’ll see in which loop you’re stuck. You’ll have to look in the manual to see how to show the call stack.