File parsing in System Verilog

In reply to dave_59:

Hi Dave,

Thanks for pointing out the potential performance issue. For my case however, the patterns are provided by vendor and mostly act as a sanity test-suite which I don’t edit or modify as of date. So each pattern will exactly translate to only one kind of test without much variations. However, I do like the idea of associative array and creating the parser one time to help provide additional flexibility in the test without need to recompile. I also need to generate some cover-groups for the test-pattern based Txn objects which I will create to help me get an up-front view of what portion of this testing is covered from vendor IP.

Thanks
Venkat