One potential problem converting the pattern file to SystemVerilog source is that you would need to recompile your source for each test, and each time you changed a test. That might present a performance problem.
A better approach would be to read in the file a line at a time and either use the UVM’s Regular Expression DPI code to pattern match the commands, or use $sscanf to parse the line. It might help to scan just the command string at the beginning of the line and use that as in index into an associative array to format scanning in the rest of the line. For example, something loike
int code;
string line, command;
string cmd_format[string] = '{
"cmd1":"cmd1 { %x, %x, %x }",
"cmd2":"cmd2 { %x, %x, %x, %x }"
};
code = $sscanf(line,"%s",command);
if (cmd_format.exists(command))
code = $sscanf(line,cmd_format[command],a[0],a[1],a[2],a[3],a[4],a[5],... a[max]);
else
$error("bad command");