File operation in SystemVerilog

SystemVerilog
, ,
1

Hi,

I have to open few files randomly from the test case. If i choose to pass the paths of those files through a environment variable, how can i operate on those files. Below is the way i am doing,
Ex:

     //assigning path to a variable
      env_var= a/b/abc.txt

      //in testcase
      file=$getenv(env_var);
        /*
          $fopen(); and other tasks
        */

Am i doing the right way. If this can be done using any other method please share it here.

Thanks.

2

In reply to Sravan Reddy k:
$getenv is not part of any standard Some tool or someone would have to provide it as a PLI application. But since getenv() is pard of the C standard library, you can import it into SV.

module top;
  import "DPI-C" function string getenv(input string env_name);
  string HOME;
  initial begin
    HOME = getenv("HOME");
    $display("$HOME = %s\n", HOME) );
  end
endmodule
3

Can this approach be used to access an env variable in `include to access different paths rather then hard-coding them ?

Something like :

`include “{getenv(HOME)/abc.sv”

4

In reply to sjain12:

No. Compiler directives get processed before executing any SystemVerilog code.

But since file pathnames are specific to the OS/platform your tool runs on, you may be able to write

`include "${HOME}/abc.sv"

You’ll need to check your tool’s user manual or contact them for support.