False assertion failure due to incorrect sampling

SystemVerilog
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1

I have written the following property/assertion to check stability of 2 signals:

property ref_clk_stable;
@(posedge clk) ($stable(tb.top.REF_CLK2_P) & $stable(tb.top.REF_CLK2_N));
endproperty

assert_ref_clk2_stable: assert property (ref_clk2_stable)
else $error(“assert_ref_clk2_stable failed.”);

In initial block I am forcing both the signals to create a true case. However the assertion is failing at first posedge of clk.

Please help me to find a solution.

2

In reply to pRoSpEr:

$stable(…) only makes sense if you’ve already sampled a past value (i.e. start checking on the second clock edge). At the first sampling event, the past value of a signal will be the default value of its type (0 for bit, X for logic, leftmost literal for enum, etc.). You could rewrite it to:


property ref_clk_stable;
@(posedge clk) ##1 ($stable(tb.top.REF_CLK2_P) & $stable(tb.top.REF_CLK2_N));
endproperty

This way you delay your comparison by a clock cycle.

P.S. It’s also nicer to use logical AND (&&) instead of bitwise AND (&).