Hi,
I have a question about the UVM factory overriding with parameterization. More precisely, I am trying to the the following “trick” (simplified example):
// Declare base component which is instantiated and created somewhere in my testbench hierarchy
class my_base_component extends uvm_component;
`uvm_component_utils(my_base_component)
...
// Derive new type which has one additional class parameter
class my_derived_component #(parameter int PARAM = 1) extends my_base_component;
`uvm_component_param_utils(my_derived_component)
...
// Somewhere in test (before super.build_phase call), override the my_base_component type with the my_derived_component type, but tune the parameter to be 6.
my_base_component::type_id::set_type_override(my_derived_component#(6)::get_type(), 1);
But, when I have placed the debug print in the my_derived_component to print out PARAM value, I can see from the log that PARAM remains “1” although I tried to give value of “6” for it the factory override call.
Just wonder whether I should be able to give the another parameter value for the class specification in the factory override or not?
Thanks!
-ilia