In reply to ilia:
The problem is with your use of the `uvm_component_param_utils macro. You need to include the parameters in the reference.
`uvm_component_utils(my_base_component#(PARAM))
It is a good idea to leave the default parameter setting out of the class declaration. Then you would have gotten a compiler error.
class my_derived_component #(parameter int PARAM) extends my_base_component;
`uvm_component_param_utils(my_derived_component) // would have generated a compiler error.
It is unfortunate that SystemVerilog uses my_derived_component not to mean the generic template class, but instead to mean my_derived_component#(), which is a class specialization using the defaults for all parameters.
By removing the default parameter assignments, that forces the user to supply an override with each class reference.