Error when using a constant as bit-select

SystemVerilog
,
1

Hello everyone,

I don’t know why for some reason, it doesn’t work when I use a constant as a bit-select in SystemVerilog.


const int one =1;
const int two =2;
const logic MyVector[int];
MyVector[one] = 1;
MyVecotr[two] = 2;

the error that is displayed is : expecting ‘:’ , found ‘]’

2

In reply to Yasmine4:

You have declared MyVector as constant, which prevents you from making any changes to it, hence the error. Remove the ‘const’ qualifier from MyVector and everything works.

3

In reply to cgales:

In reply to Yasmine4:
You have declared MyVector as constant, which prevents you from making any changes to it, hence the error. Remove the ‘const’ qualifier from MyVector and everything works.

Hello cgales,
thank you for your answer, but I tried that and it still displays the same error sadly.

4

In reply to Yasmine4:

The code modified as I mentioned works for me. If you post a complete example and the exact error message, I can take another look.

Working code:


module test();
const int one =1;
const int two =2;
logic MyVector[int];

  initial begin
    MyVector[one] = 1;
    MyVector[two] = 2;
  end
endmodule

This is likely a tool related issue, so you will need to contact your vendor support team.

5

In reply to cgales:

Also please see How to create a Minimal, Reproducible Example - Help Center - Stack Overflow

6

In reply to cgales:

In reply to Yasmine4:
The code modified as I mentioned works for me. If you post a complete example and the exact error message, I can take another look.
Working code:


module test();
const int one =1;
const int two =2;
logic MyVector[int];
initial begin
MyVector[one] = 1;
MyVector[two] = 2;
end
endmodule

This is likely a tool related issue, so you will need to contact your vendor support team.

Hello cgaeles,
it worked when I added the initial begin end block, I wonder why ? I thought that I can still assign values to variables using continuous assignment, this is what I did with the indices, and it worked for them, I don’t know why it didn’t work for the array assignment,
and by the way, I kept the “const” keyword, and it still works.

7

the final code which works looks like this:


package pack1;
typedef bit[1:0] type1[];
//this part works so fine
  onst int zero = 0;
  const int one = 1;   
  const int two = 2;   
  const int three = 3;   
  const int four  = 4;   
  const int five  = 5;   

const type1 MyVector[int];
//this part doesn't work unless I use the initial begin block
initial begin
 MyVector[zero] = {0,0};
 MyVector[one] ={0,1};
 MyVector[two] ={1,0};
 MyVector[three] ={1,1};
 MyVector[four] = {0,0};
 MyVector[five] ={0,1};
end
endpackage
8

In reply to Yasmine4:

This is why wee need to see complete examples.

Your original code snippet had procedural assignments which are only allowed within the context of a procedural code block. They are not continuous assignments without using the assign keyword. However, it is illegal to an associative array element as the target of a continuous assignment.

9

In reply to dave_59:

In reply to Yasmine4:
This is why wee need to see complete examples.
Your original code snippet had procedural assignments which are only allowed within the context of a procedural code block. They are not continuous assignments without using the assign keyword. However, it is illegal to an associative array element as the target of a continuous assignment.

In attempt to paraphrase what you said:

  • In order to assign values to variables, we do it using continuous assignments. one exception exists though.
    *the exception is associative arrays: assignment of associative arrays must definitely be done using procedural assignments, hence, inside a procedural block

I hope that I understood it correctly. so that we can mark the issue as solved.