Error when using a constant as bit-select

SystemVerilog
,
4

In reply to Yasmine4:

The code modified as I mentioned works for me. If you post a complete example and the exact error message, I can take another look.

Working code:


module test();
const int one =1;
const int two =2;
logic MyVector[int];

  initial begin
    MyVector[one] = 1;
    MyVector[two] = 2;
  end
endmodule

This is likely a tool related issue, so you will need to contact your vendor support team.