Error: simpleadder_sequencer.svh(12): (vlog-2163) Macro `uvm_object_utils_begin is undefined

UVM
1

I am getting this error for my design simpleadder. any one please explain how tp remove that.

2

You need to `include “uvm_macros.svh” to get all UVM macro definitions. SystemVerilog does not store macros in packages.

3

In reply to dave_59:

ok…thank you very much

4

In reply to manjunathkarpur:

Hi Dave,

As this question is resolved i want to know, why a sequencer is registered with object_utils? Since sequencer is a component extended from uvm_sequencer, why doesn’t it through error? And is it valid to use in this way??