class seq_item extends uvm_sequence_item;
rand bit [3:0] a;
rand bit [3:0] b;
rand bit [1:0] mode;
bit [7:0] out;
uvm_object_utils_begin(seq_item) uvm_field_int (a,UVM_ALL_ON)
uvm_field_int (b,UVM_ALL_ON) uvm_field_int (mode,UVM_ALL_ON)
uvm_field_int (out,UVM_ALL_ON) uvm_object_utils_end
function new (string name=“seq_item”);
super.new(name);
endfunction
endclass
Error-[SE] Syntax error
Following verilog source has syntax error :
Token ‘uvm_sequence_item’ should be a valid type. Please check
whether it is misspelled, not visible/valid in the current context, or not
properly imported/exported.
“seq_item.sv”, 1: token is ‘;’
class seq_item extends uvm_sequence_item;
^
Please help me identify the error the the reason.?