Hi all
i am a beginner in uvm. please correct me if the testbench is wrong or there is better solution
the error message is (Error-[MFNF] Member not found
driver.sv,
“this.req.”
Could not find member ‘addr’ in class ‘uvm_sequence_item’ ) while running vcs
i am confused with the error, because addr is defined in the class mem_seq_item.
here is my code.
class mem_seq_item extends uvm_sequence_item;
//data and control fields
rand bit [3:0] addr;
rand bit wr_en;
rand bit rd_en;
rand bit [7:0] wdata;
bit [7:0] rdata;
//Utility and Field macros,
`uvm_object_utils_begin(mem_seq_item)
`uvm_field_int(addr,UVM_ALL_ON)
`uvm_field_int(wr_en,UVM_ALL_ON)
`uvm_field_int(rd_en,UVM_ALL_ON)
`uvm_field_int(wdata,UVM_ALL_ON)
`uvm_object_utils_end
//Constructor
function new(string name = "mem_seq_item");
super.new(name);
endfunction
//constaint, to generate any one among write and read
constraint wr_rd_c { wr_en != rd_en; };
endclass
class mem_sequencer extends uvm_sequencer#(mem_seq_item);
`uvm_component_utils(mem_sequencer)
//constructor
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
endclass
Calling of build phase
class mem_sequence extends uvm_sequence#(mem_seq_item);
`uvm_object_utils(mem_sequence )
//`uvm_sequence_utils(mem_sequence,mem_sequencer)
//Constructor
function new(string name = "mem_sequence");
super.new(name);
endfunction
// virtual function void build_phase(uvm_phase phase)
//
// req = mem_seq_item::type_id::create("req");
//
// endfunction
virtual task body();
req = mem_seq_item::type_id::create("req");
// wait_for_grant();
req.randomize();
send_request(req);
// wait_for_item_done();
endtask
endclass
`define DRIV_IF pointer_to_interface.DRIVER.driver_cb
class mem_driver extends uvm_driver;
`uvm_component_utils(mem_driver);
virtual mem_if pointer_to_interface;
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db #(virtual mem_if)::get(null, "*","pointer_to_interface", pointer_to_interface))
$fatal("Failed to get BFM");
endfunction : build_phase
task run_phase(uvm_phase phase);
phase.raise_objection(this);
forever begin
seq_item_port.get_next_item(req);
drive();
seq_item_port.item_done();
end
phase.drop_objection(this);
endtask : run_phase
virtual task drive();
`DRIV_IF.wr_en <= 0;
`DRIV_IF.rd_en <= 0;
@(posedge pointer_to_interface.DRIVER.clk);
`DRIV_IF.addr <= req.addr;
if(req.wr_en) begin
`DRIV_IF.wr_en <= req.wr_en;
`DRIV_IF.wdata <= req.wdata;
@(posedge vif.DRIVER.clk);
end
if(req.rd_en) begin
`DRIV_IF.rd_en <= req.rd_en;
@(posedge vif.DRIVER.clk);
`DRIV_IF.rd_en <= 0;
@(posedge vif.DRIVER.clk);
req.rdata = `DRIV_IF.rdata;
end
endtask : drive
endclass
class mem_agent extends uvm_agent;
//declaring agent components
mem_driver driver;
mem_sequencer sequencer;
//mem_monitor monitor;
// UVM automation macros for general components
`uvm_component_utils(mem_agent)
// constructor
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
// build_phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
driver = mem_driver::type_id::create("driver", this);
sequencer = mem_sequencer::type_id::create("sequencer", this);
endfunction : build_phase
// connect_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction : connect_phase
endclass : mem_agent
class mem_model_test extends uvm_test;
`uvm_component_utils(mem_model_test)
mem_agent agent;
mem_sequence seq;
function new(string name = "mem_model_test",uvm_component parent=null);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
agent = mem_agent::type_id::create("agent", this);
seq = mem_sequence::type_id::create("seq",this);
endfunction : build_phase
task run_phase(uvm_phase phase);
phase.raise_objection(this);
// seq.start(env.mem_agnt.sequencer);
phase.drop_objection(this);
endtask : run_phase
endclass : mem_model_test
interface mem_if(input logic clk,reset);
//---------------------------------------
//declaring the signals
//---------------------------------------
logic [1:0] addr;
logic wr_en;
logic rd_en;
logic [7:0] wdata;
logic [7:0] rdata;
//---------------------------------------
//driver clocking block
//---------------------------------------
clocking driver_cb @(posedge clk);
default input #1 output #1;
output addr;
output wr_en;
output rd_en;
output wdata;
input rdata;
endclocking
//---------------------------------------
//monitor clocking block
//---------------------------------------
clocking monitor_cb @(posedge clk);
default input #1 output #1;
input addr;
input wr_en;
input rd_en;
input wdata;
input rdata;
endclocking
//---------------------------------------
//driver modport
//---------------------------------------
modport DRIVER (clocking driver_cb,input clk,reset);
//---------------------------------------
//monitor modport
//---------------------------------------
modport MONITOR (clocking monitor_cb,input clk,reset);
endinterface
module memory
#( parameter ADDR_WIDTH = 2,
parameter DATA_WIDTH = 8 ) (
input clk,
input reset,
//control signals
input [ADDR_WIDTH-1:0] addr,
input wr_en,
input rd_en,
//data signals
input [DATA_WIDTH-1:0] wdata,
output [DATA_WIDTH-1:0] rdata
);
reg [DATA_WIDTH-1:0] rdata;
//Memory
reg [DATA_WIDTH-1:0] mem [2**ADDR_WIDTH];
//Reset
always @(posedge reset)
for(int i=0;i<2**ADDR_WIDTH;i++) mem[i]=8'hFF;
// Write data to Memory
always @(posedge clk)
if (wr_en) mem[addr] <= wdata;
// Read data from memory
always @(posedge clk)
if (rd_en) rdata <= mem[addr];
endmodule
module tbench_top;
//---------------------------------------
//clock and reset signal declaration
//---------------------------------------
bit clk;
bit reset;
//---------------------------------------
//clock generation
//---------------------------------------
always #5 clk = ~clk;
//---------------------------------------
//reset Generation
//---------------------------------------
initial begin
reset = 1;
#5 reset =0;
end
//---------------------------------------
//interface instance
//---------------------------------------
mem_if intf(clk,reset);
//---------------------------------------
//DUT instance
//---------------------------------------
memory DUT (
.clk(intf.clk),
.reset(intf.reset),
.addr(intf.addr),
.wr_en(intf.wr_en),
.rd_en(intf.rd_en),
.wdata(intf.wdata),
.rdata(intf.rdata)
);
//---------------------------------------
//passing the interface handle to lower heirarchy using set method
//and enabling the wave dump
//---------------------------------------
initial begin
uvm_config_db#(virtual mem_if)::set(uvm_root::get(),"*","pointer_to_interface",intf);
//enable wave dump
//$dumpfile("dump.vcd");
// $dumpvars;
end
//---------------------------------------
//calling test
//---------------------------------------
initial begin
run_test();
end
endmodule