Error in Questa 10.2 UVM

UVM
1

Hi Verification Experts,

I was running a code and while compileing i met with the error given below and i am not able to debugg this . so, please give some suggetions on this.

** Error: (vsim-3978) ../tbd/mc_agent.sv(66): Illegal assignment to class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_tlm_if_base #(class work.mc_interface_sv_unit::mc_xactn, class work.mc_interface_sv_unit::mc_xactn)) from class mtiUvm.uvm_pkg::uvm_analysis_imp #(class work.top/mc_xactn, class mtiUvm.uvm_pkg::uvm_tlm_analysis_fifo #(class work.top/mc_xactn))

Time: 0 ns Iteration: 0 Instance: /top File: ../test/top.sv

** Error: (vsim-8754) ../tbd/mc_agent.sv(66): Actual input arg. of type ‘class mtiUvm.uvm_pkg::uvm_analysis_imp #(class work.top/mc_xactn, class mtiUvm.uvm_pkg::uvm_tlm_analysis_fifo #(class work.top/mc_xactn))’ for formal ‘provider’ of ‘connect’ is not compatible with the formal’s type ‘class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_tlm_if_base #(class work.mc_interface_sv_unit::mc_xactn, class work.mc_interface_sv_unit::mc_xactn))’.

thanks guys

2

The thing thaty I notice is the difference between these two classes:

class work.mc_interface_sv_unit::mc_xactn

class work.top/mc_xactn

This suggests that you may have included the same class definition in two different places. Put your class definitions inside a package. See my article on [the difference between package imports and include](SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons).

If that does not help, you will need to show us more of your code.

3

In reply to johnjn87:

I am getting error similar to this
Error: (vsim-3978) tc_agent.sv(21): Illegal assignment to class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_sqr_if_base #(class mtiUvm.uvm_pkg::uvm_sequence_item, class mtiUvm.uvm_pkg::uvm_sequence_item)) from class mtiUvm.uvm_pkg::uvm_seq_item_pull_imp #(class work.v::tc_transaction, class work.v::tc_transaction, class mtiUvm.uvm_pkg::uvm_sequencer #(class work.v::tc_transaction, class work.v::tc_transaction))
Error: (vsim-8754) tc_package.sv(21): Actual input arg. of type ‘class mtiUvm.uvm_pkg::uvm_seq_item_pull_imp #(class work.v::tc_transaction, class work.v::tc_transaction, class mtiUvm.uvm_pkg::uvm_sequencer #(class work.v::tc_transaction, class work.v::tc_transaction))’ for formal ‘provider’ of ‘connect’ is not compatible with the formal’s type ‘class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_sqr_if_base #(class mtiUvm.uvm_pkg::uvm_sequence_item, class mtiUvm.uvm_pkg::uvm_sequence_item))’.

I am designing a simple VIP .The error is coming in the tc_agent.sv file. The error line is actually is the connection phase
line 21: tc_d.seq_item_port.connect(tc_seqr.seq_item_export);

What should I do???

4

In reply to dip0:

The original poster never came back with a response to what their problem was - there are many different reasons that you could be getting this error. I suspect your problem is different, but showing us the code would help a lot.

I suspect you are connecting a sequencer and driver and have not parameterized them with the same sequence_item class.

5

In reply to dave_59:

Hello Dave,
here is the agent code where I get the error.
class tc_agent extends uvm_agent;
`uvm_component_utils(tc_agent)
tc_driver tc_d;
tc_monitor tc_m;
tc_sequencer tc_seqr;

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
super.build_phase(phase);
tc_d=tc_driver::type_id::create(“tc_d”,this);
tc_m=tc_monitor::type_id::create(“tc_m”,this);
tc_seqr=tc_sequencer::type_id::create(“tc_seqr”,this);

endfunction:build_phase

function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
tc_d.seq_item_port.connect(tc_seqr.seq_item_export);
//tc_m.

endfunction:connect_phase
endclass:tc_agent
Thanks for a quick reply. I really appreciate this.

6

In reply to dip0:

The driver code
class tc_driver extends uvm_driver;
`uvm_component_utils(tc_driver)
virtual intf dut_vi; //virtual interface
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
endfunction:build_phase

task run_phase(uvm_phase phase);
forever
begin
tc_transaction tx;
@(posedge dut_vi.clock);
seq_item_port.get_next_item(tx); //the get_next_item is synchronus to the start_item()
dut_vi.a<=tx.a;
dut_vi.comma<=tx.comma;//pin wiggles for the DUT
dut_vi.enable<=tx.enable;
//dut_vi.out=tx.out;
seq_item_port.item_done();//transaction is complete
end //this signals the sequencer that transaction is complete
//it //this tells the sequencer to return
endtask:run_phase

endclass:tc_driver

===============================
The sequence code
class tc_sequence extends uvm_sequence;
`uvm_object_utils(tc_sequence)
tc_transaction tc_tr;
function new(string name=“tc_sequence”);
super.new(name);
endfunction:new

task body();
//tc_transaction tc_tr;
tc_tr=tc_transaction::type_id::create("tc_tr");
//`uvm_do(tc_tr)
repeat(100)
begin
  start_item(tc_tr);  //the start_item returns

     //the driver is ready to recive the transaction
     //this synchronize the driver with the sequencer
      assert(tc_tr.randomize());
     //tc_tr.cmd=READ; read (use enum)
  finish_item(tc_tr);
end

endtask:body
function void report_phase(uvm_phase phase);
//if(tc_tr.randomize)
  // $display("the randomization is successfull");
endfunction:report_phase

endclass:tc_sequence
//--------------------------------------
//the sequencer

typedef uvm_sequencer#(tc_transaction) tc_sequencer;

========================================
The test class

class tc_test extends uvm_test;
`uvm_component_utils(tc_test)

tc_env tc_e;

function new(string name, uvm_component parent);
super.new(name,parent);
endfunction:new

function void build_phase(uvm_phase phase);
super.build_phase(phase);
//tc_env tc_e;
tc_e=tc_env::type_id::create(“tc_e”,this);

endfunction:build_phase

task run_phase(uvm_phase phase);
tc_sequence tc_seq;
phase.raise_objection(.obj(this));
tc_seq=tc_sequence::type_id::create(“tc_seq”,this);
//assert(tc_seq.randomize());
tc_seq.start(tc_e.tc_ag.tc_seqr);
phase.drop_objection(.obj(this));
endtask:run_phase

endclass:tc_test

7

In reply to dip0:

You should have gotten the following warning which I wish people would promote to an error.

** Warning: driver.sv(3): (vlog-2181) Use of a parameterized class uvm_driver as a type creates a default specialization.

You have

class tc_driver extends uvm_driver;

which should be

class tc_driver extends uvm_driver#(tc_sequence);
8

In reply to dave_59:

Hello Dave,
Should I parametrize the other classes too???

9

In reply to dip0:

I have done
class tc_driver extends uvm_driver #(tc_sequencer);
and
class tc_sequence extends uvm_sequence #(tc_transaction);

but still
warning comming like :
Warning: (vsim-3764) tc_package.sv(36): Stand-alone call to function ‘get’ treated as implicit void cast.

and the error is still same.

10

In reply to dip0:

The package class

I think the error is in the agent class in line 21 where the connection phase is coded.


package v;
import uvm_pkg::*;
`include "uvm_macros.svh"

`include "tc_transaction.sv"
`include "tc_sequence.sv"
`include "tc_driver.sv"
`include "tc_monitor.sv"
`include "tc_agent.sv"
`include "tc_env.sv"
`include "tc_test.sv"
endpackage:v