Enum default initial value

SystemVerilog
1

Hi,

the definition of the default initial value for enums in Table 6.7 of the 1800-2012 standard left me with the following questions:

if the default initial value of an enum is the base type default initial value, what happens if this value is not part of the initial enum definition:

example: enum logic [1:0] {IDLE, ONE,TWO,THREE} t1;

default inital value 'x is not part of the enum

second example enum int {v1=42, v2} t2;

defualt inital value of int is not specified, what is the default value of the enum?

Please help me, especially if you know how this is handled in some specific tool.

Johannes

2

x, 0

It is possible for an enum to have a value that is not in the value set.

3

In reply to shalom:

Thanks. Is this “It is possible for an enum to have a value that is not in the value set.” somewhere explicitly mentioned in the 1800-2012 standard? Do you know if the current versions of Modelsim and NCsim honor the standard in this aspect? I am asking because we just had an issue where the simulator set the initial default value of the enum not to 'x but to the leftmost constant in the enums value set.
If the enums value is not in the value set, doesn’t this change the type of the enum, since the value set defines the type?

4

In reply to schemmel:

  1. For example, the LRM says, “Casting can be used to perform an assignment of a different data type, or an out-of-range value, to an enumerated type.”

  2. No, this does not change the data type. The value set does not define the base data type of the enum, only a set of names and associated values that are legal assignment values in simple assignments.

5

This is what happens when you have language design by committee.

Originally, enumerated were strongly typed. They could have only the values defined by their labels, and their initial value was the first label. But then people (most likely hardware engineers) wanted to manipulate individual bits of the enum. But trying to do type checking while assigning to a bit-select of an enum variable would have been very difficult. They also wanted to have their enum variables come up in the X state without having to explicitly specify that. So the default initial value was changed to be the base data type default.

So unless you have linting tools, it is now difficult to rely on the strong typing of enums in SystemVerilog. Some tools now even ignore the remaining assignment restrictions.

It’s possible that vendors have not kept up with all the changes, you will have check with each one of them.

6

In reply to dave_59:

Yes, this is exactly the problem. Enums violate strong typing in the 1800-2012 standard. To make it worse, the tools report violations inconsistently:

enum int {a=3} ea;
enum int {b=6} eb;

initial eb=ea;

produces the following warning:
ncvlog: *W,ENUMERR (test.sv,7|7): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.

But at initialization, both enums get assigned 0 as the default value of their base type, without any warning.
So similar violations of typing rules get reported differently.

7

In reply to schemmel:

SV 3.1a said that the initial value of an enum is the first value in the list, but that was changed way back in SV-2005.