Enum default initial value

SystemVerilog
6

In reply to dave_59:

Yes, this is exactly the problem. Enums violate strong typing in the 1800-2012 standard. To make it worse, the tools report violations inconsistently:

enum int {a=3} ea;
enum int {b=6} eb;

initial eb=ea;

produces the following warning:
ncvlog: *W,ENUMERR (test.sv,7|7): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.

But at initialization, both enums get assigned 0 as the default value of their base type, without any warning.
So similar violations of typing rules get reported differently.