Empty Range if left_bound>right_bound

SystemVerilog
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1

Is it expected that bins will not be created if during range mentions left_bound>right_bound?

bins range[] = {[31:1], [63:32],[95:64],[127:96],[159:128],[191:160],[223:192],[254:224]};

I checked LRM for keywords right bound, left bound and empty range. I cannot find this restriction.

2

In reply to prashantg:

The LRM is following rules defined for a value range

If the bound to the left of the colon is greater than the bound to the right, the range is empty and contains no values.

The proposed 1800-2023 LRM adds a cross-reference to that section to maker it clearer that covergroups are using those rules.

3

In reply to dave_59:

Thanks, Dave for the reference. Apparently, I was not searching correct keywords. What are the tools’ expectations if they encounter such coding, Warnings, Fatal, etc?

4

In reply to prashantg:

The range is empty and contains no values.

Probably merits a lint type of warning.

5

In reply to dave_59:

Thanks Dave.