Embeding SVA modules inside interfaces

SystemVerilog
1

Hello!!

I have a library of verification modules (SV modules containing SVAs) that I would like to easily reuse in different test benches.
As some of these modules are related to protocols, I would like to bind a verification module inside an interface instance.
NB: I know that I could embed the assertions in the interface, but my idea is really to reuse some pre-existing SVA modules.

I was thinking about adding the SVA module binding statement inside the interface but it doesn’t seem to work. That’s too bad cause I’d really want to embed
My SVA module inside the interface. Thus with the good parameters in the interface, I can control the assertion/coverage of my verification module etc.

Then I thought, ok I can bind the SVA module to the interface instance. It’s not embedded but that’s not too bad.I tried the typical binding way I use to connect SVA modules to modules, but it doesn’t work again.

Does anyone have any idea to achieve this?

Thanks a lot in advance!

2

The SV LRM states that an interface cannot contain a module, so I suspect that will be the root cause of your problem.

However, an interface can contain other interfaces, therefore changing your verification modules to interfaces might be the way to go, provided that the verification modules do not contain a module hierarchy.

3

Can you change your verification modules to verification interfaces? Then you can bind your verification interfaces into other modules or interfaces.

4

Hello,

Thanks for your replies. I think my only solution is to turn the modules into interfaces.
This won’t solve all of my problem since I’m not sure how to pass signals through the interfaces hierarchy. I’ll dig into this.

Thanks!
BR

5

In reply to Andreas38:

Your interfaces can have ports that work exactly like module ports.

6

In reply to dave_59:

Thanks a lot Dave! It Works perfectly now!