Duplicate typedef definitions

SystemVerilog
, ,
2 

package A;
        typedef bit [7:0] t_dyn_byteArray[];
endpackage

package B;
        typedef bit [7:0] t_dyn_byteArray[];
endpackage

package C;
        import A::*;
        import B::*;

         A::t_dyn_byteArray foo;
endpackage

One other piece of unsolicited advise, be careful with your 2 t_dyn_byteArray typedefs, since they are declared independently they are considered 2 separate types, so having a single ‘global’ type may actually be your best bet