Dumping vcd files in a UVM test

In reply to cgales:

I’m using modelsim, what do you mean by the simulator’s native logging format ?

Also in this thread,https://verificationacademy.com/forums/systemverilog/running-tcl-commands-within-my-systemverilog-testbench
there is a suggested solution to solve my problem by running transcript commands from within my testbench
If you have an answer, I’d appreciate it a lot

sorry for the much disturbance