Running tcl commands from within my systemverilog testbench

SystemVerilog
, , ,
1

Hello,
I’m asking about a method to run simulator-based tcl commands from within a systemverilog testbench
I mean I want to stop the simulation using $stop, then running a transcript commands like:
vcd files test.vcd
…
…
…
run -all

Then resuming the normal test

Is this possible ?

2

Modelsim/Questa and probably other tools, have a way of accessing the Tcl commands using a DPI package. However reading your other question, I assume this requirement is no longer needed.

BTW,

3

Thanks Dave for you response, but I have now a workaround for my problem
I’ve inserted $stop functions in my code in places where I need to switch on and off VCD files dumping
Then I run my test not by hitting the “run all” button from the GUI, instead I have a TCL .do file to run my test with the first statement in it “onbreak resume” so that I make sure all the following commands(in the .do file) are executed when $stop is called from within the code.
The only remaining issue is to synchronize the $stop calls with the statements in the .do file which isn’t a big problem
Below is a sample of the .do file:
onbreak resume
vcd files src_dut.vcd;
vcd files sink_dut.vcd;
vcd add -file src_dut.vcd -r /toplevel/src_dut/core/dig/;
vcd add -file sink_dut.vcd -r /toplevel/sink_dut/core/dig/;
vcd off src_dut.vcd;
vcd off sink_dut.vcd;
run -all;
vcd on src_dut.vcd;
run -all;
vcd on sink_dut.vcd;
run -all;
vcd off sink_dut.vcd;
run -all;
vcd off src_dut.vcd;
run -all;

I’ve did it yesterday and intended to post it for anyone who may need it in the future