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Dumping vcd files in a UVM test

UVM 5357
uvm 125 VCD 1 systemverilog 9 vcd_files 1 dumpfile 1
Mustafa
Mustafa
Forum Access
22 posts
March 02, 2015 at 7:44 am

Hello,
I've a UVM test that is run from a top-level module using run_test() function.
I want to dump some signal values(inside a certain module)in a vcd file from within the test using the following system tasks:

      $dumpfile ("src_dut.vcd"); //VCD file name
      $dumpvars (1, toplevel.src_dut.core_top); //hierarchical reference to the module whose signals are to be dumped


The problem is "toplevel" isn't visible within the test scope, so I can't make the above hierarchical reference
Anyone knows haw to overcome this ?

Thanks in advance

Replies

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Mustafa
Mustafa
Forum Access
22 posts
March 02, 2015 at 7:56 am

In reply to Mustafa:

I know I can make a virtual interface(that is visible within the test)and assign the required signals to its ports, but do I have to make VIF to each module that I want to dump its signals ?!
And how to dump signals within a module recursively ?

Solution

Solution

cgales
cgales
Forum Moderator
1503 posts
March 02, 2015 at 9:40 am

You should put the VCD dump commands in an initial block in the top level of your testbench and not in the UVM environment. This way, you can have direct access to your DUT and you won't need to worry about hierarchical access out of your UVM environment.

Mustafa
Mustafa
Forum Access
22 posts
March 02, 2015 at 9:57 am

In reply to cgales:

Thank you for your response, but:
Isn't there any way to put it in the test, i.e. in the environment ?
I don't want to modify the toplevel module according to each different testcase

Mustafa
Mustafa
Forum Access
22 posts
March 02, 2015 at 10:03 am

In reply to Mustafa:

I mean I have different variables to be dumped in each different test. The toplevel module will need to be modified each time
Also variables dumping is switched on and off according to the test scenario

cgales
cgales
Forum Moderator
1503 posts
March 02, 2015 at 10:47 am

In reply to Mustafa:

Why would you change the variables being logged on a per-test basis? I would expect that if you are dumping VCD files, then you are only dumping the signals from your DUT. I would maintain the same set of signals for each test.

If you want to dump variables from your environment, I would strongly recommend using your simulator's native logging format.

Mustafa
Mustafa
Forum Access
22 posts
March 02, 2015 at 11:00 am

In reply to cgales:

I'm using modelsim, what do you mean by the simulator's native logging format ?

Also in this thread,[url=]https://verificationacademy.com/forums/systemverilog/running-tcl-commands-within-my-systemverilog-testbench[/url]
there is a suggested solution to solve my problem by running transcript commands from within my testbench
If you have an answer, I'd appreciate it a lot

sorry for the much disturbance

cgales
cgales
Forum Moderator
1503 posts
March 02, 2015 at 11:28 am

In reply to Mustafa:

Modelsim has the capability to log signals in a compressed data format which is extremely efficient. This is recommended over VCD logging since VCD files are text based and not compressed.

Read the Modelsim user manual for more information about logging signals and viewing waves. Since the Modelsim native logging format is optimized for simulation, you can typically log your entire environment with minimal overhead. This can save you the trouble of having to determine ahead of time what you want to log and change it for each test.

Of course, if you have an extremely large environment, you may not want to log every signal, but it works very well for small environments.

Mustafa
Mustafa
Forum Access
22 posts
March 02, 2015 at 11:38 am

In reply to cgales:

Ok, but one last question:
What about stopping the test, running a command within the transcript then resuming the test again ?
Do you know a method to do such thing ?

cgales
cgales
Forum Moderator
1503 posts
March 02, 2015 at 11:53 am

In reply to Mustafa:

I would need to know more about what you are trying to accomplish. Typically, your run script will have everything configured when started and there would be no need to stop the test and do anything external.

Mustafa
Mustafa
Forum Access
22 posts
March 02, 2015 at 12:26 pm

In reply to cgales:

For example, I was doing the following manually in the transcript(the run times below are based on signal events)
vcd files basic_scenario_rx.vcd basic_scenario_tx.vcd
vcd add -file basic_scenario_tx.vcd -r /toplevel_top/src_dut/CORE/*
vcd add -file basic_scenario_rx.vcd -r /toplevel_top/sink_dut/CORE/*
vcd off basic_scenario_tx.vcd
vcd off basic_scenario_rx.vcd
run 1440926.34ns
--------------------
vcd on basic_scenario_rx.vcd
run 39996.93ns
--------------------
vcd on basic_scenario_tx.vcd
run 94380.84ns
-------------------
vcd off basic_scenario_tx.vcd
run 10977.95ns
---------------------
vcd off basic_scenario_rx.vcd

What I want is to do:
run -all
Then within the systemverilog testbench, I want to invoke the above transcript commands

Thank you for your interest

cgales
cgales
Forum Moderator
1503 posts
March 02, 2015 at 1:11 pm

In reply to Mustafa:

I highly recommend enabling all recording at time 0 and continuing through to the end of simulation. Using the native recording features of Modelsim is very efficient and removes the need to try and enable/disable at specific times. By recording everything for the entire simulation, you can then easily focus on the areas of concern.

Mustafa
Mustafa
Forum Access
22 posts
March 03, 2015 at 11:06 pm

In reply to cgales:

Hi cgales,
This may be a solution and does what I desire
you may check it here

Thanks for your concern

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