Driving with and without clocking blocks

SystemVerilog
,
8

In reply to curious_learner:
Comments

  1. Verilog is a language that is a bit too loose in structures and rules, and it allows you to easily get into trouble.
  2. SystemVerilog 1800’2017 provided new constructs to avoid many of those loose rules to introduce errors, particularly at the RTL level.
  3. DEFINITELY read 1800’2017 section 9.2 Structured procedures
  4. Of particular interest 9.2.2.2.2 always_comb compared to always @*
    Variables on the left-hand side of assignments within an always_comb procedure, including
    variables from the contents of a called function, shall not be written to by any other processes, whereas always @* permits multiple processes to write to the same variable.
    Thus,

always @* a = d;
always @* a = !d; // THAT IS LEGAL
always_comb w=d;  // OK, but error if another assignment
always @* w = !d; // illegal
//variable 'w' driven in a combinational block, may not be driven by any other process.
  1. 9.2.2.4 Sequential logic always_ff procedure
    The always_ff procedure can be used to model synthesizable sequential logic behavior. For example:
always_ff @(posedge clock iff reset == 0 or posedge reset) begin
r1 <= reset ? 0 : r2 + 1;
...
end

The always_ff procedure imposes the restriction that it contains one and only one event control and no blocking timing controls. Variables on the left-hand side of assignments within an always_ff procedure, including variables from the contents of a called function, shall not be written to by any other process.
Thus,

always @(posedge clk or posedge reset) begin
//Allowed !!!
if (reset) q <= 1'b0; // See below error message if always _ff is used
else  q <= d;
end
// FF Better
always_ff @(posedge clk or posedge reset) begin
// Variable 'q' driven in an always_ff block, may not be driven by any other process
if (reset) q <= 1'b0;
else  q <= d;
end
  1. Use type “logic” instead of “reg”

Recommendations: Use SystemVerilog coding styles that enforces more structured coding rules and guidelines to avoid “weird” stuff in the execution of the code. In that respect, SystemVerilog got to a closer approachment to VHDL, which is more structured and has stricter rules than Verilog.
Test code that you play with
Edit code - EDA Playground

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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