Driving with and without clocking blocks

SystemVerilog
,
7

In reply to ben@SystemVerilog.us:

Thanks Ben, this was certainly helpful.
For the moment lets consider the following code:

  1. qb is a reg which is assigned continuously. (I read this is not allowed)
  2. q is a reg procedurally assigned from 2 different always blocks. (I read that the same reg cannot be assigned from 2 different always blocks)

yet this compiles with no issue if we try on EDA playground. Could you help me understand why?


// Design
// D flip-flop
module dff (clk, reset,
  d, q);
  input      clk;
  input      reset;
  input      d;
  output     q;
  reg        qb;
  reg        q;

  assign qb = ~q;

  always @(posedge clk)
  begin
      // Assign D to Q on positive clock edge
      q <= d;
  end
  
  always @(posedge reset)
  begin
    if (reset) begin
      // Asynchronous reset when reset goes high
      q <= 1'b0;
    end
  end
endmodule

// Testbench
module test;

  reg clk;
  reg reset;
  reg d;
  wire q;
  wire qb;
  
  // Instantiate design under test
  dff DFF(.clk(clk), .reset(reset),
          .d(d), .q(q) );
          
  initial begin
    // Dump waves
    $dumpfile("dump.vcd");
    $dumpvars(1);
    
    $display("Reset flop.");
    clk = 0;
    reset = 1;
    d = 1'bx;
    display;
    
    $display("Release reset.");
    d = 1;
    reset = 0;
    display;

    $display("Toggle clk.");
    clk = 1;
    display;
  end
  
  task display;
    #1 $display("d:%0h, q:%0h,",
      d, q);
  endtask

endmodule

Same code can be run on EDA playground at this link : Your text to link here…

Thanks for the help!