Driving an internal net in UVM

UVM
,
1

Hello Everyone,

I have an internal net called wire P_HOOK under a design. My requirement is to drive this signal in UVM sequence
How do i do that

so far i did



interface test1 (input clk);

logic p_hook;

endinterface

bind design_top: `DUT.design_top_test1 test1_0 (
.p_hook(`DUT.design_top.u_vdiv.P_HOOK)
);

When i try to access this in my uvm sequence


class test_sequence extends uvm_sequence ...

virtual test1 vif;

task drive ();
vif.p_hook = 1'b1;
endtask

endclass

I get the following error : Usage of ‘vif.p_hook’ inconsistent with ‘net’ object.

Can anyone tell what i am doing wrong

Thanks

2

In reply to tejasakulu:

Never drive a signal form a sequence or test. There is no timing synchronization. You have to do this from the driver.

3

In reply to chr_sue:

Do what ?

4

In reply to tejasakulu:

A sequence does not have signals. It is class and it has data members.
I believe you want to make your sequence dependent on an internal state right?

5

In reply to chr_sue:

Sorry for the late reply.

Now i understood your post #1, i should do this in my driver; sequence should be kept independent of the driving the signals.

does my code make sense ? if i put that piece of code in driver instead of sequence.

Thanks,
Tejas

6

In reply to tejasakulu:

A general remark: forcing an internal signal in your design is a very dangerous thing. You should do this only during development to check something.
The code you are showing does not have an relationship to any time or clock cycles. This will not do what you are expecting.