Drive a "reg" using continuous assign

SystemVerilog
,
1 

module tb_top();
reg bmult;
logic cmult;
wire awire = 'b1;

initial begin

	#1ns;
	assign cmult = awire; //'b1;
	assign bmult = awire; //'b1;
	$display("bmult = %0d, cmult = %0d", bmult, cmult);
end
endmodule

Result:
bmult = 1, cmult = 1

Question:
Is it legal to drive a variable of datatype “reg” using “assign” (continuous assignment).

2

In reply to natasv:

There are differences between continuous assignments, procedural assignments, and procedural continuous assignments. They are all described in Chapter 10 of the LRM.

Your code is demonstrating procedural continuous assignments, and not continuous assignments. It will work, but only you can determine if what you are doing meets your requirements.

3

In reply to cgales:

Thank you.
In that case, if I bring the assign statement outside of the initial block, the assignment becomes continuous assignment. Is this true?
The assignment in the below code also passes compilation. I expected to see that continuous assignment of “reg” is invalid. Why is this the case?


module tb_top();
reg breg;
logic clogic;
wire awire = 'b1;

initial begin
	#1ns;
	assign clogic = awire; //Procedural Continuous assignment 
	#1ns;
	$display("breg = %0d, clogic = %0d", breg, clogic);
end
	assign breg = awire; //Continuous assignment
endmodule
4

In reply to natasv:

Why would you expect that the continuous assignment to “reg” is invalid?

From section 10.3 of the LRM:
Continuous assignments shall drive values onto nets or variables, both vector (packed) and scalar. This
assignment shall occur whenever the value of the right-hand side changes.

A “reg” is just a variable type.