Drive a "reg" using continuous assign

SystemVerilog
,
3

In reply to cgales:

Thank you.
In that case, if I bring the assign statement outside of the initial block, the assignment becomes continuous assignment. Is this true?
The assignment in the below code also passes compilation. I expected to see that continuous assignment of “reg” is invalid. Why is this the case?


module tb_top();
reg breg;
logic clogic;
wire awire = 'b1;

initial begin
	#1ns;
	assign clogic = awire; //Procedural Continuous assignment 
	#1ns;
	$display("breg = %0d, clogic = %0d", breg, clogic);
end
	assign breg = awire; //Continuous assignment
endmodule