Don't cares compare

SystemVerilog
1

Hi,
I have switch case in which I want to compare different lengths of prefixes:

bit [7:0] compare 
case (compare)
8'b000_0_0101 : do A 
8'b010_0_0101 : do B
8'b001_1_0??? : do C
default : do D
endcase

my problems is in the last case before the default, every combination starts with 5’b001_1_0 should hit the third case but using questions mark in the suffix doesn’t work and it goes to the default, is there any way to make it work?

Thanks!

2

In reply to moshiko:

You want to use casez statement instead of a plain case statement. “casez” uses a convention that a bit that is “z” is a don’t-care (the ? character in a numeric literal is the same as a z).

3

In reply to moshiko:

Nevermind,
I found the solution, replacing case with casex

Thanks!

4

In reply to moshiko:

Avoid using casex. When using 4-state expressions, an X bit in the case expression becomes a don’t care the same in the case item.

Use casez instead, even better is using case () inside. The latter uses the asymmetric equality operator ==? so that only X or Z in the case item become don’t cares.