Document generator for system verilog and uvm files

SystemVerilog
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Does anyone use any document generators like Doxygen or natural docs to automatically generate parameter definitions or register fields from system verilog files? or is it still preferred to manually write word documents? Any good experiences? Seems like there is a lot of support for c#,java and python wondering what’s the hardware equivalent?

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In reply to GPR:

See Natural docs for UVM | Verification Academy

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In reply to dave_59:

Thanks Dave, I saw those threads before posting the question, but was looking for user feedback on larger soc designs, does it really work? It seems more like a college project tool rather than a standard tool. Did you use it?

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In reply to dave_59:

Hello Dave, i am curious to know if there is any best proven document generators supporting System Verilog & UVM? please share your experiences

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In reply to neel07:
https://verificationacademy.com/forums/systemverilog/document-generator-system-verilog-and-uvm-files#reply-90442