In reply to simonsabato:
SystemVerilog requires all hierarchical references to be bound at elaboration. There would have to be optimization rules to skip the binding. This might be doable at some point in the future with a generate-if construct, but more difficult with a procedural-if construct.
A suggestion for you is creating two ram module wrappers, one wrapping each implementation, and using a Verilog config construct to select the ram on a per instance basis. See See section 33 of 1800-2017 LRM and this paper: https://lcdm-eng.com/papers/snug01_verilog2000.pdf