Disadvantage of logic

SystemVerilog
,
1

What can be the disadvantage of using logic data type variables in class based test bench environment?

2

In reply to bachan21:

one example

logic is a 4 state data type (0,1,x,z) vs bit being a 2 state data type (0,1)

rand logic datain
vs
rand bit datain

makes a difference as randomization is compute heavy

3

In reply to hsam:

So are you saying that logic makes computation harder (there by less speed)?

4

In reply to bachan21:
makes a difference as randomization is compute heavy

This is not correct. Randomization only works with 2-state values.

Unless you are working with very large objects, there is not much difference between 2-state and 4-state datatypes in terms of performance and capacity. You need 4-state values if you have to deal with Z-states, or need to check that X values have not propagated to the outputs. But for most stimulus generating classes, you only need 2-state data types.

5

In reply to dave_59:

Hi dave,
We can declare randomizable variable with logic datatype, right?