Difference between nettype and "wire logic"

SystemVerilog
,
5

In reply to dave_59:

Hi Dave,

Thanks for your answers i write one simple program as shown below but i was unable to use the resolution function. Could you please give me the code on how can i use the resolution function in this case.

typedef struct {
real field1;
real field2;

} T;

function automatic T Tsum
(input T driver);
//Tsum.filed1 = 0.0;
foreach(driver[i])
Tsum.field1 += driver[i].field1;
endfunction

// a nettype whoose data type is T and resolution function is Tsum
nettype T wTsum with Tsum;
module foo (foo_p);
output wTsum foo_p;
wTsum q;

assign q=foo_p;
assign foo_p = T’{14.5,2.5};

endmodule