Difference between forcing and writing a register

UVM
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1

Hi Forum,
Can some one tell.
what is the difference between direct rtl signal forcing and register writing using backdoor(RAL) from the below
case1


   cfg.xtal.source_sel.freq_sel.set(0);
   cfg.xtal.source_sel.write(status,cfg.xtal.source_sel.get(),"backdoor",this);

case 2


   force {top1.i_xtal.xtal_slv.freq_sel} = 1'b0;

internally definition of freq_sel is like this.


uvm_reg_field freq_sel;
freq_sel = new("freq_sel", "RW", 1, 19, {`TOP1,".i_xtal.xtal_slv.reg_x26_bit3"}) 
void'(add_field(freq_sel ));

I see both 1 & 2 results the same value, but what is the difference between these two here?
From this link I understood forcing a dut signal

How to correlate the backdoor register write with the case 2 force!

Thanks
Abhishek

2

In reply to Abhishek E:

Backdoor writing via RAL is usually not the same as SystemVerilog force. It is a deposit; a procedural assignment to a signal which could be overwritten by a later assignment. A force cannot be overwritten until it is released, or forced to another value.

For case 2 I think you meant to write

force `TOP1.i_xtal.xtal_slv.reg_x26_bit3 = 1'b0;

freq_sel was the name of the uvm_reg_field class.

If you modify any register, whether it be by a force, or any normal DUT operation that does not go through a monitored interface, the only way to keep the RAL model correlated is performing a frontdoor or backdoor read of that register.

3

In reply to dave_59:
Thanks for the explanation

Hi Dave,
Can you please elaborate “If you modify any register, whether it be by a force, or any normal DUT operation that does not go through a monitored interface”.

4

In reply to Abhishek E:

The two key principles behind RAL is the testbench having a mirror database of all the registers in the DUT, and mapping addresses on an interface bus to hardware registers. That database has to be kept in sync with the DUT. The only way it does that is by executing a RAL read/write operation, or by monitoring transactions on that interface bus. Any other access outside those and the database becomes out of sync.

A force on a register would cause the database to become out of sync until something tries to read that register.