Difference between forcing and writing a register

In reply to Abhishek E:

Backdoor writing via RAL is usually not the same as SystemVerilog force. It is a deposit; a procedural assignment to a signal which could be overwritten by a later assignment. A force cannot be overwritten until it is released, or forced to another value.

For case 2 I think you meant to write

force `TOP1.i_xtal.xtal_slv.reg_x26_bit3 = 1'b0;

freq_sel was the name of the uvm_reg_field class.

If you modify any register, whether it be by a force, or any normal DUT operation that does not go through a monitored interface, the only way to keep the RAL model correlated is performing a frontdoor or backdoor read of that register.